Interfaces between multiple ICs of a single system are useful for a variety of applications. These applications include computer interfaces between CPU and Dynamic Random-Access Memory (DRAM) (including Double Data Rate Synchronous DRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM protocols), Systems-in-Package (SiPs), and other IC-to-IC interfaces.
Nevertheless, synchronizing such multiple IC systems presents a number of challenges. On a large IC, a clock tree may be used to ensure that a clock signal propagates throughout the chip in a manner that controls the timing skew of clock signals as they reach various clocked components, such as registers. Such clock trees are often balanced separately for each IC in a multiple IC system. After balancing, each clock tree may include an independently derived number of buffers providing an independently designed amount of delay. Circuits within each IC's input and output paths may also cause timing delay, and these circuits may include Electro-Static Discharge (ESD) protection circuits, voltage level shifters, input drivers, and output drivers. The delays of these input and output path circuits and the delays of each of the clock tree buffers may vary with independently varying Process, Voltage, and Temperature (PVT) variations of each IC. The delays of the clock tree buffers balance timing skew of clock signals delivered to clocked features of each respective IC. However, balancing clock skew on an individual chip level may not guarantee low clock skew over the multiple ICs in a multiple IC system.